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Achieving Low power with Active Clock Gating for IoT in IPs
Chaitanya Kamasani,ASIC DESIGN ENGINEER -II,Synopsys Inc.,INDIA
Biography :
Chaitanya immediately after his masters from NIT Trichy joined Synopsys India on 2015. He has been working as an ASIC Design Engineer for USB products. His areas of interest includes low power designs such as Clock Gating, UPF and design optimization.

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